Since the late 1960s, a new generation of integrated circuits has been developed approximately every four years. Each generation has been characterized by roughly a 30 percent reduction in device dimensions, resulting in a two-fold density increase over the preceding generation. Increases in circuit density have been consistently limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is directly related to its resolution capability. The sum of minimum feature width (F) and minimum space width (S) producible with a given piece of photolithographic equipment is referred to in this disclosure as "minimum pitch". Since, for practical purposes, F can be considered to be equal to S, minimum pitch is, therefore, approximately equal to double the minimum feature width, or 2F. Using contemporary photolithography techniques, one line (feature) and one space may be defined for a given minimum pitch.
It has long been recognized, by those skilled in the fabrication of integrated circuits, that vertical layers as thin as 0.01 .mu.M can be grown with a high degree of accuracy. By comparison, the minimum feature size, producible with the present generation of photolithography equipment used to produce 1-megabit SRAMs and 4-megabit DRAMs, is approximately 0.7 .mu.m. Therefore, utilizing contemporary equipment in conjunction with contemporary photolithography techniques, approximately 1.4 .mu.m (the minimum pitch) is required to define one line and one space.
Isolated vertical layer segments may be formed by depositing an expendable layer on a substrate, masking and etching the expendable layer down to the substrate such that expendable layer remnants having vertical sidewalls are created, blanket depositing a thin spacer layer over the substrate and expendable layer remnants, performing an anisotropic etch to create vertical, thin-layer segments (in the form of spacer strips) on the sidewalls of the expendable layer, and then etching away the expendable layer remnants to leave the spacer strips. In the early 1980s, Seiki Ogura, Christopher F. Codella, Nivo Rovedo, Joseph F. Shepard and Jacob Riseman of IBM Corp. used this technique to create a half-micron-width gate for an insulated-gate field-effect transistor (IGFET).
If a process could be devised in which IGFETs (also commonly, but inaccurately, called MOSFETs) could be fabricated on both longitudinal vertical edges of rectangularly-shaped mesas (raised islands of silicon) using a spacer etch to create the gates thereof, circuit density could be increased dramatically by a factor of at least two.